1. Field of the Invention
The present invention relates to a carrier structure embedded with semiconductor chips and a method for manufacturing the same, and, more particularly, to a carrier structure used to avoid both a warp of the carrier structure and burr formation when cutting metal, and a method for manufacturing the same.
2. Description of Related Art
Customer demands of the electronics industry continue to evolve rapidly and the main trends are high integration and miniaturization. In order to satisfy those requirements, especially in the packaging of semiconductor devices, development of circuit boards with the maximum of active and passive components and conductive wires has progressed from single to multiple layer types. This means that a greater circuit layout area is available due to interlayer connection technology.
In the conventional semiconductor device, semiconductor chips are mounted on top of a substrate, and then processed in wire bonding, or connecting the semiconductor chip which has the solder bump thereon to the conductive pads on the substrate, followed by disposing solder balls on the bottom surface of the substrate to provide electrical connections for printed circuit board. Although an objective of high quantity pin counts is achieved, this condition is limited by way of long pathways of conductive circuits making electric characteristics unable to be improved in the high frequency and high-speed operating situations. Otherwise, the complexity of the manufacture is only relatively increased because too many connective interfaces are required for conventional semiconductor packages.
In many studies, semiconductor chips directly conducting to external electronic devices are embedded into a package substrate to shorten conductive pathways, decrease signal loss and distortion, and increase abilities of high-speed operation.
In a carrier structure embedded with a semiconductor chip, as shown in FIG. 1, metal layers 15 are disposed on electrode pads 13 of an active surface of the semiconductor chip 12 for preventing destruction of the semiconductor chip 12 in a carrier 11 by laser ablation to form via holes for manufacturing a circuit built-up structure 16. The carrier structure embedded with a semiconductor chip includes: a carrier 11, on which a cavity is formed; a semiconductor chip 12 which is placed in the cavity, and has a plurality of electrode pads 13 formed on an active surface thereof; a passivation layer 14 formed on the semiconductor chip 12, and accordingly exposing the a plurality of electrode pads 13; a plurality of metal layers 15 formed on surfaces of the electrode pads 13; and a built-up structure 16 formed on surfaces of the semiconductor chip 12 and the carrier 11. The built-up structure 16 is formed on the surfaces of the semiconductor semiconductor chip 12 and the carrier 11, and conducts to the electrode pads 13 of the semiconductor chip 12.
Currently, in a carrier structure embedded with semiconductor chips, the carrier is generally made of organic resins such as bismaleimide-triazine (BT), and then, that carrier is cut by a cutting tool to become a carrier structure having a single semiconductor chip. However, stress on the surface of the built-up structure and on that of the non-built-up structure is not the same. Because the built-up structure 16 is asymmetric, the carrier becomes warped. Under this condition, production becomes complex, and excessively warped carriers cause low yield and low stability of products. Alternatively, if the carrier is made of metal, it has better strength for anti-warp than the resin carrier. However, after the metal carrier is cut by a cutting tool, metal burrs will be generated thereby causing disadvantages such as poor appearance of the carrier structure and damage of the cutting tool, furthermore the metal burrs will also be generated thereby causing damage of the carrier structure embedded with semiconductor chips.